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Slave Port Interface
Table 8-3. Invalid mailbox organization
MSB Address
MSB
LSB
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
Variable 1 (MSB)
Variable 2 (MSB+2)
Variable 3 (MSB+2)
Variable 5 (MSB)
Variable 6 (MSB+2)
Variable 8 (MSB)
Variable 10 (LSB)
Variable 14
(LSB)
(LSB)
(LSB)
(LSB)
(LSB)
(LSB)
Variable 11
Variable 15
Variable 2 (MSB)
Variable 3 (MSB)
Variable 4 (MSG)
Variable 6 (MSB)
Variable 7 (MSB)
Variable 9
Variable 12
Variable 16
(MSB+1)
(MSB+1)
(LSB)
(MSB+1)
(LSB)
Variable 10 (MSB)
Variable 13
Variable 17
Table 8-3 highlights the improperly aligned variables. Depending on when reads and writes occur, it is
possible that the master and CPU would see inconsistent values.
The four-byte read buffer is cleared when an I 2 C STOP condition occurs or when the SPI SSB signal is
deasserted, depending upon which port is in use. Contents are replaced whenever the register address
increments from one row to the next.
8.3.2
Binary semaphore (mutex) operation
The MMA955xL platform includes two semaphore registers that can be used by the CPU and system
master to negotiate ownership of shared assets. These can be mailbox registers or any other shared item.
These registers can be read by only one of the two parties at any point in time. Simultaneous attempts will
be serialized by the module.
Each semaphore register has several possible actions associated with it, as shown in Table 8-4 .
Table 8-4. Semaphore actions
Semaphore content
0x00
0x01
0x02
0x00
0x01 or 0x02
Action
Read 0x00
Read 0x01
Read 0x02
Write any value (Normally, this is
only done by the current owner.)
Side effect
Set semaphore = 1. Reader now has ownership of shared asset.
None. Slave host has ownership of the semaphore.
None. CPU has ownership of the semaphore.
Set semaphore = 0 - No action
Set semaphore = 0 - Ownership has been relinquished
The actions in Table 8-4 are atomic, assuring that the CPU and master can unambiguously negotiate
ownership of any asset.
Operation of the two semaphore registers is identical, allowing for simultaneous negotiations of two
different sets of shared assets.
A classic problem with operation of semaphores occurs when the owner of a shared asset fails to relinquish
control, resulting in a “lockout” situation. For this reason, each semaphore has an optional “time-out”
register. If enabled, a countdown timer is initiated to the specified value whenever the semaphore is set.
The counter then begins counting down. When it hits zero, an interrupt is issued. The CPU should then
clear the semaphore.
Each timer is stopped whenever the associated semaphore is cleared.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
123
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